Arrays - detect signal changes and simulate in Modelsim

1. You've probably found the hiddeous (imho) std_logic_2d_t decleared in an altera package that is used when you define a 2d array in a bdf file and convert it to VHDL. Please avoid at all costs.

Be aware that quartus is not properly standards compliant and will let you get away with some things that modelsim will complain about. (this is probably down to the fact that verilog works and the underlying logic works so why let a few VHDL rules get in the way!)

2. I still stand by your logic outputting 0. You can monitor ANY signal in signaltap - where did you read such lies?