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Altera_Forum
Honored Contributor
Honored ContributorArrays - detect signal changes and simulate in Modelsim
I have two problems with a 1-d array I'm using. The array's cells are 64 bit vectors. Declaration: package my_pack is
type commands_array is array (natural range <>) of std_logic_vecto...
Altera_ForumHonored Contributor
Honored ContributorHey Tricky, once again, thanks for your help.
1. To be honest, this error is from an HDL file created by Quartus from the BDF file that is my top entity (something I feel like I should have mentioned). I am very surprised that Quartus did this, and that my design actually compiles (and works). I deleted the "63 downto 0" completely (since the array is declared as an array of vectors with 64 bits, so it seems unnecessary) and it seems to compile, and simulate. Haven't checked on the arrays yet, if I have a problem I will ask. 2. The arrays (I took both input and output on purpose) are not red, they're black. Like I said, it's impossible that they are zero, because there is a signal that receives a small part of the cell's value (8 bits out of the 64, each one at a time), and I see from this signal that the arrays are okay. They are also not initialized automatically, and I checked them at various points in time, and they always seem to be zero, so that is weird. A question though, I saw that if I have a signal that is defined outside of a process I cannot monitor it in SignalTap. Why is that?
