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Altera_Forum's avatar
Altera_Forum
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12 years ago

array slice, type mismatch

I have a 1D-array of std_logic_vector, with 9 elements. I have another 2D array of std_logic_vector, 2x7 elements. I want to take a slice of the 9 element 1D array, and put it in the 2D array. I need elements 1-7 and want to put it in (1,1 to 7) and then elements 3-9 and put it in (2,1 to 7).

I get the following error: Target type arr12 in signal assignment is different from expression type arr11.

If I the declare arr13 as type arr11 it does not complain, but I only want a 7 element 2D array not 9.

_______________________________________________________________

type arr11 is array (1 to 9) of std_logic_vector(11 downto 0);

type arr12 is array (1 to 7) of std_logic_vector(11 downto 0);

type arr13 is array (1 to 2) of arr12;

signal datain : arr11;

signal dataout: arr13;

process(s_clk)

begin

for jj in 1 to 2 loop

if (s_clk'event and s_clk='1') then

s_dataout(jj)(1 to 7) <= s_datain(1 to 7);

end if;

end loop;

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Assuming s_dataout and s_datain are the same as datain and dataout, you forgot the first index in the s_datrain index. You have also indexed s_dataout in the wrong direction (its declared 11 downto 0, but you are indexing 1 to 7, which is not allowed).

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Yes, s_dataout, and s_data in are the same as datain and dataout (that was a typo). The value s_datain(1) is of type std_logic_vector(11 downto 0), the value s_dataout(1) is of type std_logic_vector(11 downto 0);

    s_datain = [12'b sample1, 12'b sample2, 12'b sample3, 12'b sample4, 12'b sample5, 12'b sample6, 12'b sample7, 12'b sample8, 12'b sample9]

    s_dataout = (1)[sample1, sample2, sample3, sample4, sample5, sample6, sample7]

    s_dataout = (2)[sample3, sample4, sample5, sample6, sample7, sample8, sample9]

    The index DOES work if I declare, signal dataout : arr11, then when I choose s_datain(1 to 7) it is put in s_dataout(1 to 7) correctly, but I have 8,9 which I don't need. All I'm trying to do is take a slice of samples from a 1D array and put it in a smaller 2D array.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Sorry I misread the first code.

    Anyway, the problem is because datain is of type arr11, not arr12. arr13 is an array of arr12. So you need to convert the slice to arr12:

    s_dataout(jj)(1 to 7) <= arr12( s_datain(1 to 7) );
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    There is another way to get this problem resolved by using unconstrained types which where introduced with VHDL 2008. 

    
TYPE std_2dim_at IS ARRAY (natural RANGE <>) OF std_logic_vector;
TYPE std_3dim_at IS ARRAY (natural RANGE <>) OF std_2dim_at;
SIGNAL datain  : std_2dim(1 TO 7)(11 DOWNTO 0);
SIGNAL dataout : std_3dim(1 TO 2)(1 TO 7)(11 DOWNTO 0);
...

    This way all signals are derived from the same types and you don't need to cast the types anymore when assigning one signal to the other.