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Altera_Forum's avatar
Altera_Forum
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13 years ago

Array of wires as memory lookup

Hello all, I am quite new to Verilog, and I am trying to implement a memory array in a particular manner. Multiple addresses in the array need to point to the same location in physical memory, ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Create an address translation function and use it to map the addresses in every place you access memory.

Try to keep the logic simple. 

function  addressTranslation;
input  addrIn;
begin
if (addrIn >= 9'h20 && addrIn < 9'80) addressTranslation = addrIn - 9'20
else addressTranslation = addrIn;
end
endfunction