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Altera_Forum's avatar
Altera_Forum
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13 years ago

Array of wires as memory lookup

Hello all,

I am quite new to Verilog, and I am trying to implement a memory array in a particular manner. Multiple addresses in the array need to point to the same location in physical memory, I was thinking perhaps I could use an array of wires.

The actual question:

How best I map a wire to these locations in memory if I define a wire like so: 

wire  mem ;
And say I wish to map from 'h20 to 'h7F in mem to 0 to 'h5F in a 2d reg defined as follows: 

reg  data ;
My attempt: 

assign mem  = data ;
But of course this is illegal.

Of course if there is a more elegant solution I would be very interested.

Your assistance would be much appreciated.

Regards,

Jovian.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    You cannot implement memory with wires. Wires in Verilog represent interconnections or bit groupings and do not retain state. To implement memory you must use registers or a memory block instance.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    What if you created a memory and then modified the decoder so that on reads to certain addresses they get re-directed to the same phyical address?

    Before going too far down this road, what are you trying to accomplish?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Create an address translation function and use it to map the addresses in every place you access memory.

    Try to keep the logic simple. 

    function  addressTranslation;
input  addrIn;
begin
if (addrIn >= 9'h20 && addrIn < 9'80) addressTranslation = addrIn - 9'20
else addressTranslation = addrIn;
end
endfunction