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Remember that in Verilog, all loops will be unrolled. What is being generated here is logic to set all array elements to 0 in one clock tick. Everything in the for loop body will get a separate hardware allocated for it. If that is what you must have, then fine, but keep in mind that a lot of logic will be used up to do this. The overhead in this example isn't too bad. It could be huge if you had lots of code in the loop body.
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The code shows an initial block, not an always block, so it is setting the contents of the ram at power up.
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