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Altera_Forum's avatar
Altera_Forum
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10 years ago

Array indexing questions

Hi all, new user here, and new to verilog as well. I have some questions about indexing an array. Say I have a 16x8bit array. There will be an address input that points to which one of the 16 bytes to do action on. The trigger tells it when to do the action.

Here's the initialization stuff -

module arraymem (new_width, trigger, address, stored_width);

input trigger;

input [7:0] new_width;

input [3:0] address;

output reg [7:0] stored_width;

parameter memsize = 16;

reg [7:0] width [memsize-1:0]; //16 x 8bit internal storage array

how to declare "k"?

initial begin

for (k = 0; k <= memsize - 1; k = k + 1) //tells it to be 16 long

begin width[k] = 4'h0000; end

end

Immediately, I have a problem. The input address will be in binary form, 1111 indexing the 15th byte, 0000 indexing the 0th bye, 0010 indexing the 2nd byte, etc. But the parameter memsize where I declare that it is 16 long, it is an integer (or a non-binary at least). I want the binary input address to correspond to the proper integer parameter value, but I do not know how to do this. Any suggestions on this? I think I will start with this question before moving onto my next question. Thanks.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Just make k an integer. You limit the did and its only used in the initial block anyway, so it doesn't affect the real time hardware.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Remember that in Verilog, all loops will be unrolled. What is being generated here is logic to set all array elements to 0 in one clock tick. Everything in the for loop body will get a separate hardware allocated for it. If that is what you must have, then fine, but keep in mind that a lot of logic will be used up to do this. The overhead in this example isn't too bad. It could be huge if you had lots of code in the loop body.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    --- Quote Start ---

    Remember that in Verilog, all loops will be unrolled. What is being generated here is logic to set all array elements to 0 in one clock tick. Everything in the for loop body will get a separate hardware allocated for it. If that is what you must have, then fine, but keep in mind that a lot of logic will be used up to do this. The overhead in this example isn't too bad. It could be huge if you had lots of code in the loop body.

    --- Quote End ---

    The code shows an initial block, not an always block, so it is setting the contents of the ram at power up.