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Altera_Forum
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14 years ago

Array Indexing possible in VHDL?

Hi everyone, i have an enquiry regarding VHDL. let's say i have a 128 bits key which is split into 4 parts:

--divide the key into 4 parts    
        k0<=key(127 downto 96);
        k1<=key(95 downto 64);
        k2<=key(63 downto 32);
        k3<=key(31 downto 0);
is it possible to do something like in c language in VHDL:

k[0]=k0;

k[1]=k1;

k[2]=k2;

k[3]=k3;

where k[] is a 4 element array...i am aware that the bus width is uneven issue but is there anyway to implement this in VHDL? if not any ideas how i can implement this in VHDL? thanx in advance!

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    You can create an indexed type

    type key_t is array (0 to 3) of std_logic_vector(31 downto 0);

    signal k : key_t;

    and then in your code, you can take advantage of loops too

    process(key)

    begin

    for i in 0 to 3 loop

    k(i) <= key(32*(i+1)-1 downto 32*i);

    end loop;

    end process;

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    hi dave, thank you so much for the informative reply! actually i'm trying to implement XTEA:http://en.wikipedia.org/wiki/xtea

    The following is the VHDL code i'm working on:

    
    Library IEEE;
    USE IEEE.std_logic_1164.all;
    use ieee.numeric_std.all;
    entity XTEA is    
    Port     (
        clk:in std_logic;
        input: in unsigned(63 downto 0);
        key : in unsigned(127 downto 0);
        Encoder_output,Decoder_output: out unsigned(63 downto 0)
            );
    end entity;
    architecture rtl of XTEA is
    signal k0,k1,k2,k3: unsigned(31 downto 0);
    signal     n:integer:=0;
    signal key_array: unsigned (3 downto 0);
    type key_t is array (0 to 3) of unsigned(31 downto 0);    
    signal k : key_t;
    begin
    process(clk,input)
    variable z,z_up,z_mid,z_down,z_total,y,y_up,y_mid,y_down,y_total: unsigned (31 downto 0);
    variable sum: unsigned (31 downto 0) := x"00000000";
    variable delta: unsigned (31 downto 0) := x"9e3779b9";
    variable test,test1,test2,test3 : unsigned (31 downto 0);
    variable natvar,natvar1,natvar2,natvar3 : integer;
    begin
            --divide the key into 4 parts    
            k(3)<=key(127 downto 96);
            k(2)<=key(95 downto 64);
            k(1)<=key(63 downto 32);
            k(0)<=key(31 downto 0);
        
                        
    if(rising_edge(clk)) then
        if (n=0) then
            --divide input into y and z
            y:= input(63 downto 32);
            z:= input (31 downto 0);
            --sum:=x"00000000";         -- try take this out later
            elsif (n=32) then
            --for decode:delta is delta*2^5 for 32=(2^5) round 
            sum:=delta(26 downto 0)&"00000";
            end if;
    --encode        
    if (n <32) then
    test:=sum and x"00000003";
    test1:="00000000000" & sum(31 downto 11);    --shift by 11 bits to the right
    natvar:=to_integer(test);
    natvar1:=to_integer(test1);
    z_total:=(((z(27 downto 0)&"0000") XOR ("00000"&z(31 downto 5)))+z) XOR(   sum + k( natvar  downto natvar )   );
    y:=y+z_total;
                sum:=sum+delta;
    y_total:=(((y(27 downto 0)&"0000") XOR ("00000"&y(31 downto 5)))+y) XOR (sum+ k(natvar1 downto natvar1  ) );
    z:=z+y_total;
                
                Encoder_output<=y&z;    
                
    --decode            
    elsif(n<64) then
            if(n=32) then
            sum:=delta*32;
            end if; 
    test2:=sum and x"00000003";
    test3:="00000000000" & sum(31 downto 11);    --shift by 11 bits to the right
    natvar2:=to_integer(test2);
    natvar3:=to_integer(test3);    
        
    test1:=sum and x"00000003";
    natvar1:=to_integer(test1);
    y_total:=(((y(27 downto 0)&"0000") XOR ("00000"&y(31 downto 5)))+y) XOR (sum+ k(natvar3 downto natvar3));
    z:=z-y_total;
                sum:=sum-delta;
    z_total:=(((z(27 downto 0)&"0000") XOR ("00000"&z(31 downto 5)))+z) XOR(sum + k(natvar2 downto natvar2));
    y:=y+z_total;
                Decoder_output<=y&z;
            end if;
                n<=n+1; --counter
        end if;
        
    end process;
    end rtl;
    

    Using the method you suggested, i encountered some problems:

    Error (10327): VHDL error at XTEA.vhd(59): can't determine definition of operator ""+"" -- found 0 possible definitions

    The problem lines are bolded...apparently my array (named k(0 to 3)) has the type of key_t but other operations are done in unsigned type. i tried converting k() to unsigned using "unsigned(k())" but to no avail. is there anyway to go about this? Than a lot for the great help again! have a nice day ahead!:)
  • Altera_Forum's avatar
    Altera_Forum
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    The cause of the error is different from what you assume. This expression can't work, because it results in a subarray rather than a single array element k( natvar downto natvar ). Do you mean k( natvar)?

    In addition, an expression length error is involved with sum:=delta*32;
  • Altera_Forum's avatar
    Altera_Forum
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    On another note - you're indexing into K (that has 4 elements) with a 32 bit integer. What happens when natvar2 or 3 are greater than 3?

  • Altera_Forum's avatar
    Altera_Forum
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    Thank you FvM for pointing out my mistakes. yes i meant k(natvar)...also the

    delta*32
    is not possible so i replaced it with
     delta(26 downto 5) & "00000"
    . and the code works! thank you again for your help! on a side note, i am experiencing some weird simulation waveform where by after 64 counts, the cycle repeats itself again which is not suppose to happen (circled in red)

    http://img811.imageshack.us/img811/8240/problemwy.jpg (http://imageshack.us/photo/my-images/811/problemwy.jpg/)

    ...any idea what happen?

    Thanx tricky for bringing that natvar issue up...i'll try and figure it out...sorry for my mistakes...i'm a total newbie trying to learn haha
  • Altera_Forum's avatar
    Altera_Forum
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    Apparently the integer counter is optimized to 0 to 63 range and overflows. If you want to stop operation after one pass, you should do explicitely.