Array implementation in VHDL and calculating the average of elements in the array

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-- Company:

-- Engineer:

--

-- Create Date: 18:44:30 11/26/2012

-- Design Name:

-- Module Name: average - rem_trend

-- Project Name:

-- Target Devices:

-- Tool versions:

-- Description:

--

-- Dependencies:

--

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity average is

port (

b : in std_logic_vector(31 downto 0);

data_out : out std_logic_vector(31 downto 0));

end average;

architecture rem_trend of average is

begin

process(b)

variable a1 : integer;

variable c1 : real;

begin

for i in 1 to 31 loop

b(i) := b(i-1) + b(i);

end loop;

a1 := b(31);

c1 := a1/32;

for i in 0 to 31 loop

b(i) := b(i)-(3*c1);

if (b(i) > 0) then

b(i) := 0;

end if;

end loop;

for i in 0 to 31 loop

data_out(i)<=b(i);

end loop;

end process;

end rem_trend;

I tried this code.. removed package and put std_logic_vector..it gives me 2 errors HDL parsers 800 and HDL parsers 808