Array implementation in VHDL and calculating the average of elements in the array

I tried this code

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-- Company:

-- Engineer:

--

-- Create Date: 18:44:30 11/26/2012

-- Design Name:

-- Module Name: average - rem_trend

-- Project Name:

-- Target Devices:

-- Tool versions:

-- Description:

--

-- Dependencies:

--

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use ieee.numeric_std.all;

package but is

type mat_arr is array(0 to 31) of real;

end but;

use work.but.all;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity average is

port (

data : in mat_arr;

data1 : in mat_arr;

data_out : out mat_arr);

end average;

architecture rem_trend of average is

signal my_int : mat_arr;

begin

process(data,data1,my_int)

variable a1 : real;

variable b : real;

begin

for i in 0 to 31 loop

my_int(i)<=data(i);

end loop;

a1:=0.0;

for i in 0 to 31 loop

line 59 a1:=a1+my_int(i);

end loop;

b := a1/32.0;

for i in 0 to 31 loop

my_int(i) <= my_int(i)-(3.0*b);

if (my_int(i) > 0.0) then

my_int(i) <= 0.0;

end if;

end loop;

for i in 0 to 31 loop

data_out(i)<=my_int(i);

end loop;

end process;

end rem_trend;

but it shows error at line 59... real operand is not supported in this context!!!!

please help...tomorrow is the last day for submission