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Altera_Forum
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13 years ago

Array implementation in VHDL and calculating the average of elements in the array

I have a Home assignment to be done in VHDL to find out the average of the elements of an array and then subtract thrice the average from each of the array elements. Then the elements greater than ze...
Altera_Forum's avatar
Altera_Forum
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13 years ago

You cannot add together a std_logic and a std_logic. I also suggest you never make a custom array of std_logics either. Thats what std_logic_vector is for. If you make you're own, then none of the functions that work with std_logic_vector will work with your type.