Array implementation in VHDL and calculating the average of elements in the array

I tried this code after going through that book....

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-- Company:

-- Engineer:

--

-- Create Date: 18:44:30 11/26/2012

-- Design Name:

-- Module Name: average - rem_trend

-- Project Name:

-- Target Devices:

-- Tool versions:

-- Description:

--

-- Dependencies:

--

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

package but is

type mat_arr is array(0 to 31) of std_logic;

type rem_tre is array(0 to 31) of std_logic;

end but;

use work.but.all;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity average is

port (

data : in mat_arr;

a : in integer;

data_out : out rem_tre);

end average;

architecture rem_trend of average is

begin

process(data, a)

begin

for i in 1 to 31 loop

line-50 data(i) <= data(i-1) + data(i);

end loop;

end process;

end rem_trend;

But while running in Xilinx ISE 14 I get the following error: ERROR:HDLParsers:808 - "C:/Users/vicky/array/average.vhd" Line 50. + can not have such operands in this context.

I require a quick reply. Meanwhile I'll be trying... I would be very thankful for any help