Array implementation in VHDL and calculating the average of elements in the array

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I don't know why this doesn't work and what exactly I need to add?

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Missing are

- definition of signals and variables

- declaration of port signals connecting in- and outputs

Necessary corrections (at least)

- correct VHDL assignment syntax

- correct VHDL array index syntax

- use a legal VHDL attribute instad of length[xxx]

- use synthesizable types instead of real

As you apparently missed your VHDL lectures, you should consider a good text book.