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TuckerZ's avatar
TuckerZ
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

Are Unpacked Array Supported in Platform Designer's Component Editor?

Hello, I'm trying to design an Avalon MM Slave and turn it into a component for use inside of platform designer using the component editor. In my top level HDL file, I have these two ports which ...
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  • RichardT_altera's avatar
    RichardT_altera
    3 years ago

    May I know which version of Quartus are you using, Standard or Pro?

    I'm afraid that if you are using Quartus Standard, there is limited support for the System Verilog language.

    Link: https://www.intel.com/content/www/us/en/docs/programmable/683283/18-1/verilog-and-systemverilog-synthesis-support.html

    The recommendations are as follows:

    1. Upgrade to Quartus Pro.
    2. Modify the design code by converting the multidimensional arrays into single-dimensional arrays.

    Unfortunately, the engineering team has no plans to enhance Quartus Standard.

    We apologize for any inconvenience caused by the limitations of the tool.

    Best Regards,

    Richard Tan

    Edited: Platform Designer does not support 2D arrays.

TuckerZ's avatar
TuckerZ
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

These parameters are defined in the port list. The component editor has detected them as parameters. 

module avalon_mm_adapter 
    #( 
        parameter   AVALON_BUS_WIDTH    = 32,
        parameter   NUM_CONTROL_REG     = 1,
        parameter   NUM_STATUS_REG      = 1  )
    (
        input   logic           csi_clk,       
        input   logic           rsi_n,     

        // Avalon Bus Signals
        input   logic [AVALON_BUS_WIDTH - 1 :0] avs_writedata,
        output  logic [AVALON_BUS_WIDTH - 1 :0] avs_readdata,
        input   logic [AVALON_BUS_WIDTH - 1 :0] avs_address,
        input   logic                           avs_read,
        input   logic                           avs_write,
        output  logic                           avs_waitrequest,
        output  logic                           avs_readdatavalid, 

        // non-Avalon Signal
        input   logic [AVALON_BUS_WIDTH - 1 : 0] coe_status_reg [NUM_STATUS_REG - 1 : 0],

        // control outputs to fabric 
        output logic [AVALON_BUS_WIDTH - 1 : 0] coe_control_reg [NUM_CONTROL_REG - 1 : 0]
    );