Altera_Forum
Honored Contributor
9 years agoAnyone had fitter doing bad job between partition boundaries?
Hi,
I'm working on some LL+Design Partition so I can get faster design cycles and help the design to close timing easier. so the structure I have is like this +top (logic locked) -partition 1 (child logic lock region) -partition 2 (child logic lock region) the two child logic lock region are far away from each other so I have buffers instantiated on top level. After building the design, I found that the buffer gonna be pulled to one of the LL regions. say from partition 1 to buffer -300ps slack but from buffer to partition 2 is like 4000ps slack. Do you guys know if there is any special optimization you can turn on to solve this problem? Thank you for all kinds of suggestions. Best, Joshua