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Thanks, very helpful! Do I need to consider whether clock tree is enough when I design my system?
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You don't need to consider the 'clock tree' at all. You have control over the signals and functions in a design. When you design something where you depend on a edge of a signal, it becomes a 'clock'. Whether or not a single buffer or multiple buffers are used to drive that clock is an implementation detail of the synthesis tool.
If you generate gated clocks (i.e. my_clock <= free_clock and some_signal; then you will have to deal with the consequences that will show up in the timing analysis report...regardless of how many buffers are used.
To answer your earlier question, yes you would use the Quartus power analyzer tool to determine estimated power consumption.
Kevin Jennings
Honored Contributor
