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Altera_Forum's avatar
Altera_Forum
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13 years ago

Any approach to close clock toggle?

For a design, if I want to reduce power consumption, one approach is pausing the clock toggle for a module which does not need to work in a specific period. In the design, I can use a AND gate whose ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Thanks very much. I just wonder what is the definition of clock tree? I always see it but don't understand very well. Is the specific wire inside FPGA for clock signal? How can I know whether the clock tree is enough for my design?

Thanks.