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Altera_Forum's avatar
Altera_Forum
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15 years ago

Any ALTLVDS gurus out there?

I have two non-GX alteras (Stratix II & Stratix IV) between which I need to sling some data. Each device has it's own clock domain, and I only have a one bit connection between the two. What's the best/fastest way to send data (let's say it only needs to travel in one direction) from one to the other? I got excited when I found the ALTLVDS mega function, but either I can't figure out how to make the receiver do clock recovery from the data stream, or it is not capable of doing clock recovery.

I thought maybe there might be a way to contort either a PLL or a DLL to do my clock recovery dirty work for me and generate a clock from the data, but I'm not having any luck. I have no problem putting my data through an 8B10B encoder in order to facilitate clock recovery. Has anyone else out there been in my shoes?

-Dano-

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    You should read about the soft-CDR mode provided by Stratix IV LVDS receivers. Apparently, a similar functionality isn't provided for Stratix II, although I'm under the impression, it may be possible using additional logic. A similar functionality can be even achieved with Cyclone III FPGA utilizing FPGA dynamic phase shift.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    How much data do you need to send? You might want to consider a UART. If the FPGAs generate UART sampling clocks that are a few times higher than the baud rate, you should be able to recover the data just fine. The LVDS channels can operate at up to ~1Gbps, so if you were oversampling at the receiver LVDS by 8x your baud rate could be 125MHz, and with 10 clocks or so per byte, you should hit 10Mbytes/sec ok.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    How much data do you need to send? You might want to consider a UART. If the FPGAs generate UART sampling clocks that are a few times higher than the baud rate, you should be able to recover the data just fine. The LVDS channels can operate at up to ~1Gbps, so if you were oversampling at the receiver LVDS by 8x your baud rate could be 125MHz, and with 10 clocks or so per byte, you should hit 10Mbytes/sec ok.

    In answer to your first question, I need to send as much as I can - 1GB/s would be nice. I have some fast 16 bit @80MHz A/D converters, which would be nice to be able to transmit over the link - that's ~1.3Gb/s. I've managed to get my own Manchester encoded link working at 40Mb/s, a bit shy of what I'd like, but I don't see pushing it much beyond that. The more I delve into clock recovery, the more I think it's the way to go. I just found a Xilinx app note that shows how to do a DLL using logic gates, so I'm going to give that a shot.

    Oh, one more thing - is there any way for user logic to control the frequency of a PLL's oscillator? I see an "external feedback" option in the ALTPLL Wizzard, but don't understand how to use that yet. If I had my own DLL and the ability to feed the PLL my own control signals for it's frequency, I think I could make this work. In the Xilinx example, they had to use an external VCO from Maxim to regenereate the clock, as I guess you can't break the path between the phase detector and the VCO in a Xilinx PLL (just guessing here - I no nothing about Xilinx parts). I was hoping that the Altera PLLs were flexible enough to be able to do this without me having to use an external VCO.

    -Dano-
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Regarding XAPP250, i don't see an option to use an internal Altera PLL instead of the external PLL. I also doubt that the method will work well at GBit speed, the same with other software CDR methods.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    You can control an Altera PLL frequency. The ALTLVDS component needs to be instantiated with its external PLL option enabled. You then need to instantiate the external PLL. That PLL can then be controlled via the ALTPLL_RECONFIG megafunction.

    I haven't implemented something like this though, so can't comment on how much of a pain it will be, but it is possible.

    If only you had a clock between those two FPGAs, eh!

    Cheers,

    Dave