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How much data do you need to send? You might want to consider a UART. If the FPGAs generate UART sampling clocks that are a few times higher than the baud rate, you should be able to recover the data just fine. The LVDS channels can operate at up to ~1Gbps, so if you were oversampling at the receiver LVDS by 8x your baud rate could be 125MHz, and with 10 clocks or so per byte, you should hit 10Mbytes/sec ok.
In answer to your first question, I need to send as much as I can - 1GB/s would be nice. I have some fast 16 bit @80MHz A/D converters, which would be nice to be able to transmit over the link - that's ~1.3Gb/s. I've managed to get my own Manchester encoded link working at 40Mb/s, a bit shy of what I'd like, but I don't see pushing it much beyond that. The more I delve into clock recovery, the more I think it's the way to go. I just found a Xilinx app note that shows how to do a DLL using logic gates, so I'm going to give that a shot.
Oh, one more thing - is there any way for user logic to control the frequency of a PLL's oscillator? I see an "external feedback" option in the ALTPLL Wizzard, but don't understand how to use that yet. If I had my own DLL and the ability to feed the PLL my own control signals for it's frequency, I think I could make this work. In the Xilinx example, they had to use an external VCO from Maxim to regenereate the clock, as I guess you can't break the path between the phase detector and the VCO in a Xilinx PLL (just guessing here - I no nothing about Xilinx parts). I was hoping that the Altera PLLs were flexible enough to be able to do this without me having to use an external VCO.
-Dano-
Honored Contributor
