Forum Discussion
Altera_Forum
Honored Contributor
15 years agoYou can control an Altera PLL frequency. The ALTLVDS component needs to be instantiated with its external PLL option enabled. You then need to instantiate the external PLL. That PLL can then be controlled via the ALTPLL_RECONFIG megafunction.
I haven't implemented something like this though, so can't comment on how much of a pain it will be, but it is possible. If only you had a clock between those two FPGAs, eh! Cheers, Dave