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that error indicates it is expecting a locally signal that hasnt been decalred.
Have you mapped something like this?
signal pll_ref_clk : std_logic; -- this is a local wire
pll_ref_clk => pll_ref_clk, -- this maps the port of the entity to the local wire
Your error would come around if you didnt declare the signal locally, even if the port name exists on the component.
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Okay, thank you for your reply. You prompted me to notice that I made a silly mistake by attempting to map to a port with "<=" rather than "=>." How embarrassing -- over 20 years of VHDL experience but a few recent years of not doing it.
Problem solved. Thanks a bunch.
Honored Contributor
