Altera_Forum
Honored Contributor
14 years agoannoying file reloading
Hi,
I've been getting intermittent notices while working on a particular Verilog file. This notice informs me that the file has been changed and asks me if I want to reload the file, possibly overwriting any changes. This happens when I save the file. Is there a way to turn off this notice? version: Quartus 11.1 build 173 64-bit OS: windows 7