Hi, I have following error while Analysis & Synthesis using Qyartus 21.2 and 22.2: Error(13224): Verilog HDL or VHDL error at vector_capture.sv(143): index -8 is out of range [15:0] for 's_in_data' I have added my project (vector_capture_21_2). The project can be found in vector_capture_21_2\quartus_proj and source files can be found in vector_capture_21_2\src According to my code and parameter assignments, the index cannot be -8, but I am not clear how the tool see -8 as an index. Can someone help me to overcome this issue? Thank you, Ranesh

Hi @Ranesh , The reason for the error is the value of parameter W_MODULE_DATA (256) in submodule vector_capture.sv being overridden by the value of parameter W_MODULE_DATA (16) in top-module vector_capture_synth_top.sv. Thanks, Best Regards, Sheng p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

Hi Sheng, Thank you for your answer. What you are saying is correct, but that cannot be the reason for this error message. From lines 26 and 27 of vector_capture_synth.sv 26: parameter W_MODULE_DATA = 16; // Supported data widths (8 bits to 256 bits) power of 2 (2^3 to 2^8)27: parameter W_MODULE_DESC = 204; // less than or equal to 256 From lines 66 to 70 of vector_capture.sv are: 66: localparam c_DESCBYTEALIGNBITS = ((W_MODULE_DESC % > 0) ? (8 - (W_MODULE_DESC % 8)) : 3'b0; c_DESCBYTEALIGNBITS = ((204 % > 0) ? (8 - (204 % 8)) : 3'b0 c_DESCBYTEALIGNBITS = 467: logic [((W_MODULE_DESC + c_DESCBYTEALIGNBITS) - 1):0] s_in_desc; // Configuration bus from feeder module logic [((204 + 4) -1):0] s_in_des logic [207:0] s_in_des68: localparam c_IN_DESC_BYTE_CNT = ((W_MODULE_DESC + c_DESCBYTEALIGNBITS)/8); c_IN_DESC_BYTE_CNT = ((204 + 4)/8) c_IN_DESC_BYTE_CNT = ((208)/8) c_IN_DESC_BYTE_CNT = 2669: localparam c_IN_DATA_BYTE_CNT = (W_MODULE_DATA/8); c_IN_DATA_BYTE_CNT = (16/8) c_IN_DATA_BYTE_CNT = 2 70: localparam c_OUT_DATA_BYTE_CNT = (W_MCDMA_DATA/8); c_OUT_DATA_BYTE_CNT = (256/8) c_OUT_DATA_BYTE_CNT = 32 The lines 140 and 144 are in vector_capture.sv are: 140: for (int c = c_IN_DESC_BYTE_CNT; c < c_OUT_DATA_BYTE_CNT; c++) (int c = 26; c < 32; c++) c can take only 26, 27, 28, 29, 30 and 31141: begin142: if (c < (c_IN_DESC_BYTE_CNT + (c_IN_DATA_BYTE_CNT - s_in_empty))) (c < (26 + (2 - s_in_empty))) (c < (28 - s_in_empty)) if s_in_empty is 0 c can take only 26 and 27 if s_in_empty is 1 c can take only 26 143: s_output_data[c] <= s_in_data[((W_MODULE_DATA - ((c - c_IN_DESC_BYTE_CNT) * 8)) - 1) -: 8]; If c become 26, the line becomes s_output_data[26] <= s_in_data[((16 - ((26 - 26) * 8)) - 1) -: 8] s_output_data[26] <= s_in_data[((16 - ((0) * 8)) - 1) -: 8] s_output_data[26] <= s_in_data[((16 - 0 - 1) -: 8] s_output_data[26] <= s_in_data[15 -: 8] s_output_data[26] <= s_in_data[15 : 8] If c become 27, the line becomes s_output_data[27] <= s_in_data[((16 - ((27 - 26) * 8)) - 1) -: 8] s_output_data[27] <= s_in_data[((16 - ((1) * 8)) - 1) -: 8] s_output_data[27] <= s_in_data[((16 - 8 - 1) -: 8] s_output_data[27] <= s_in_data[7 -: 8] s_output_data[27] <= s_in_data[7 : 0] 144: end From the above calculations, c cannot take any values that drives the index of s_in_data to be -8. Regards, Ranesh

Hi Sheng, Thank you for your answer. What you are saying is correct, but it cannot be the cause of this error. ========== Lines 21, 26 and 27 of vector_capture_synth_top.sv are: 21: parameter W_MCDMA_DATA = 256; 26: parameter W_MODULE_DATA = 16; // Supported data widths (8 bits to 256 bits) power of 2 (2^3 to 2^8) 27: parameter W_MODULE_DESC = 204; // less than or equal to 256 ========== Lines 66 to 70 of vector_capture.sv are: 66: localparam c_DESCBYTEALIGNBITS = ((W_MODULE_DESC % > 0) ? (8 - (W_MODULE_DESC % 8)) : 3'b0; c_DESCBYTEALIGNBITS = ((204 % > 0) ? (8 - (204 % 8)) : 3'b0 c_DESCBYTEALIGNBITS = (4 > 0) ? (8 - 4) : 3'b0 c_DESCBYTEALIGNBITS = 4 67: logic [((W_MODULE_DESC + c_DESCBYTEALIGNBITS) - 1):0] s_in_desc; // Configuration bus from feeder module logic [((204 + 4) - 1):0] s_in_desc; logic [207:0] s_in_desc; 68: localparam c_IN_DESC_BYTE_CNT = ((W_MODULE_DESC + c_DESCBYTEALIGNBITS)/8); c_IN_DESC_BYTE_CNT = ((204 + 4)/8) c_IN_DESC_BYTE_CNT = ((208)/8) c_IN_DESC_BYTE_CNT = 26 69: localparam c_IN_DATA_BYTE_CNT = (W_MODULE_DATA/8); c_IN_DATA_BYTE_CNT = (16/8) c_IN_DATA_BYTE_CNT = 2 70: localparam c_OUT_DATA_BYTE_CNT = (W_MCDMA_DATA/8); c_OUT_DATA_BYTE_CNT = (256/8) c_OUT_DATA_BYTE_CNT = 32 ========== Lines 140 to 144 of vector_capture.sv are: 140: for (int c = c_IN_DESC_BYTE_CNT; c < c_OUT_DATA_BYTE_CNT; c++) (int c = 26; c < 32; c++) Within this for loop, c can take only 26, 27, 28, 29, 30 and 31 141: begin 142: if (c < (c_IN_DESC_BYTE_CNT + (c_IN_DATA_BYTE_CNT - s_in_empty))) (c < (26 + (2 - s_in_empty))) (c < (28 - s_in_empty)) Note: s_in_empty is a single bit. Within this if statement: If s_in_empty = 0, (c < (28 - 0)) and c can be either 26 or 27 If s_in_empty = 1, (c < (28 - 1)) and c can be either 26 143: s_output_data[c] <= s_in_data[((W_MODULE_DATA - ((c - c_IN_DESC_BYTE_CNT) * 8)) - 1) -: 8]; If c takes 26 s_output_data[26] <= s_in_data[((16 - ((26 - 26) * 8)) - 1) -: 8]; s_output_data[26] <= s_in_data[((16 - ((0) * 8)) - 1) -: 8]; s_output_data[26] <= s_in_data[((16 - (0) - 1) -: 8]; s_output_data[26] <= s_in_data[((16 - 1) -: 8]; s_output_data[26] <= s_in_data[15 -: 8]; s_output_data[26] <= s_in_data[15 : 8]; If c takes 27 s_output_data[26] <= s_in_data[((16 - ((27 - 26) * 8)) - 1) -: 8]; s_output_data[26] <= s_in_data[((16 - ((1) * 8)) - 1) -: 8]; s_output_data[26] <= s_in_data[((16 - (8) - 1) -: 8]; s_output_data[26] <= s_in_data[((8 - 1) -: 8]; s_output_data[26] <= s_in_data[7 -: 8]; s_output_data[26] <= s_in_data[7 : 0]; 144: end From the above calculations, c cannot take any values that drives index of s_in_data to be -8. Regards, Ranesh

Hi @Ranesh , I further create a test case with minimized code. I'm getting synthesis error Error(13224): Verilog HDL or VHDL error at test.sv(19): index -8 is out of range [15:0] for 's_in_data' as you mentioned before in Quartus Pro v21.2 check image: I further test with Vivado v2022.1. I'm also getting the similar synthesis error [Synth 8-524] part-select [-1:-8] out of range of prefix 's_in_data' check image: I further found out that the root cause is at variable s_in_empty in module vector_capture.sv. You can't use logic type s_in_empty in for loop if statement. If change the type of variable s_in_empty from logic to for example parameter, both Quartus and Vivado can successfully synthesis the code check image: Therefore, I believe this is expected behavior. Thanks, Best Regards, Sheng p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

Analysis & Synthesis Error(13224): Verilog HDL or VHDL error "..:" index -8 is out of range [15:0]..

24 Replies

FvM
Super Contributor
3 years ago
Hi Ranesh,

as written above, dependency of variable part select on s_in_empty causes the problems. You can easily check by commenting out s_in_empty. I don't attempt to decide if System Verilog requires an indirectly dependant part select to be calculated correctly by Quartus compiler or not.

In any case, the problem can be easily bypassed by a direct comparison of the actual part select index against a constant limit.

for (int c = c_IN_DESC_BYTE_CNT; c < c_OUT_DATA_BYTE_CNT; c++)
begin
int idx = W_MODULE_DATA - ((c - c_IN_DESC_BYTE_CNT) * 8);
if ((c < (c_IN_DESC_BYTE_CNT + (c_IN_DATA_BYTE_CNT - s_in_empty))) && idx >= 8 )
s_output_data[c] <= s_in_data[((W_MODULE_DATA - ((c - c_IN_DESC_BYTE_CNT) * 8)) - 1) -: 8];
end

Best regards
Frank
ShengN_altera
Super Contributor
3 years ago
Hi Ranesh,

Below is the expert explanation on the second example (s_outbytecount):
s_output_data[d] <= s_in_data[((W_MODULE_DATA - ((d - s_outbytecount) * 8))- 1) -: 8]; //vector_capture_v2.sv, line number 151
In this case, array index uses logic type variable "s_outbytecount", for which synthesis generates a circuit which ensures no out of bound error happens.
In original use case, when local param is used in the index operation, they are replaced with actual values in compile time, so all possible indices get generated which cause out of bound error during loop unrolling.
e.g.
s_in_data[((W_MODULE_DATA - ((c - c_IN_DESC_BYTE_CNT) * 8)) - 1) -: 8]
Here, c is running from 16 to 31. During loop unrolling, index value is generated for all values of c which causes out of range error.

If you need further detailed explanation, may be we can set up a meeting after January 3rd with internal expert where they can explain the concept of index range being known at compile time.

Thanks,
Best regards,
Sheng

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Analysis & Synthesis Error(13224): Verilog HDL or VHDL error "..:" index -8 is out of range [15:0]..

24 Replies

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