Analysis & Synthesis Error(13224): Verilog HDL or VHDL error "..:" index -8 is out of range [15:0]..

Hi Ranesh,

as written above, dependency of variable part select on s_in_empty causes the problems. You can easily check by commenting out s_in_empty. I don't attempt to decide if System Verilog requires an indirectly dependant part select to be calculated correctly by Quartus compiler or not.

In any case, the problem can be easily bypassed by a direct comparison of the actual part select index against a constant limit.

for (int c = c_IN_DESC_BYTE_CNT; c < c_OUT_DATA_BYTE_CNT; c++)
begin
int idx = W_MODULE_DATA - ((c - c_IN_DESC_BYTE_CNT) * 8);
if ((c < (c_IN_DESC_BYTE_CNT + (c_IN_DATA_BYTE_CNT - s_in_empty))) && idx >= 8 )
s_output_data[c] <= s_in_data[((W_MODULE_DATA - ((c - c_IN_DESC_BYTE_CNT) * 8)) - 1) -: 8];
end

Best regards
Frank