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Ranesh's avatar
Ranesh
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3 years ago

Analysis & Synthesis Error(13224): Verilog HDL or VHDL error "..:" index -8 is out of range [15:0]..

Hi, I have following error while Analysis & Synthesis using Qyartus 21.2 and 22.2: Error(13224): Verilog HDL or VHDL error at vector_capture.sv(143): index -8 is out of range [15:0] for 's_in_da...
ShengN_altera's avatar
ShengN_altera
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3 years ago

Hi @Ranesh ,

Internal Feedback:

For the expression if (c < (c_IN_DESC_BYTE_CNT + (c_IN_DATA_BYTE_CNT - s_in_empty)))

1. When "s_in_empty" is of type logic, the expression in if condition can't be evaluated at compile time. So all possible indices are generated for "s_in_data".

e.g., for value of c = 18 onwards, index for s_in_data becomes negative.

Let me further check with expert on the second example you provided.

Thanks,

Best Regards,

Sheng

Ranesh's avatar
Ranesh
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3 years ago

Hi Sheng,

Please note that the expression if (c < (c_IN_DESC_BYTE_CNT + (c_IN_DATA_BYTE_CNT - s_in_empty))) is bound by the expression for (int c = c_IN_DESC_BYTE_CNT; c < c_OUT_DATA_BYTE_CNT; c++). This limits c not to be below c_IN_DESC_BYTE_CNT, which is 26. So in the expression s_output_data[c] <= s_in_data[((W_MODULE_DATA - ((c - c_IN_DESC_BYTE_CNT) * 8)) - 1) -: 8], which is bound by the expression that you have mentioned, c can only be 26 or 27, because s_in_empty is single bit signal and c_IN_DATA_BYTE_CNT = 2.

I am re-attaching my explanation in word document for you and the expert

Regards,

Ranesh