Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

An problem about using M4K

In my design I generate a dual port RAM using megafunction which shows the resources estimate is 144 M4K. Also ,I designed an array of shift registers like this :

reg [11:0] IQ_taps[0:1020];

always @(posedge CLK)//generate shift registers

begin

for (i = 0; i < 1020; i = i + 1)

begin

IQ_taps[i]<=IQ_taps[i+1];

end

IQ_taps[1020]<=IQ;

end

reg signed[11:0] IQ_corr[0:255];

always @(posedge CLK) // do the operation

begin

for (k = 0; k < 256; k = k + 1)

begin

case (CORR_CODE[k])

1'b1:

IQ_corr[k] <= IQ_taps[k*4];

1'b0:

IQ_corr[k] <= -IQ_taps_2[k*4];

endcase

end

end

I am sure the M4K is only used in these two entity.

After "Analysis & Synthesis" ,the summary indicates total memory bits of 602618 is used. But the fitter failed and an error appeared in the message window:

"Error: Selected device has 250 RAM location(s) of type M4K RAM. However, the current design needs more than 250 to successfully fit."

Since only 602618 memory bits is used ,why need more than 250 M4K to successfully fit??

By the way , I used EP2C70F672C6 in my design.

Thanks,

Tigre

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Hi,

    Just a quick question.

    how do you get IQ_taps_2.

    If this a registered copy of IQ_taps then you are doubling the resource.

    edit: though this doesn't explain it as each IQ_taps needs 3 M4K blocks
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Hi,

    Actually there is no IQ_taps_2 ,I just forgot to recover this IQ_taps_2 to IQ_taps when presenting this M4K problem.

    I ever tried to decompose a single 1020 shift registers to two 510 shift registers, so the IQ_taps_2 is introduced to represent the second 510 shift registers and the IQ_taps represent the first 510 shift registers . But this way didn't work and I got the same error when fitting .

    A dual port RAM used 144 M4K, Can a 1020 shift registers need more than 100 M4K?

    I can't solve this problem . Can anyone help me??

    Thanks!

    Tigre
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    I think I have found the reason.

    The fitter report shows this array of shift registers are synthesized into two SYNCRAM. One has the port width of 510 bits and depth of 3 ,the other has the port width of 5610 bits and depth of 2. But M4K can only support port width of 36 bits.

    So the problem turns to be : how to make QUARTUS synthesize this array of 1020 shift registers to M4K with port width of 16 bits??

    always @(posedge CLK)

    begin

    for (i = 0; i < 1020; i = i + 1)

    begin

    IQ_taps[i]<=IQ_taps[i+1];

    end

    IQ_taps[1020]<=IQ;

    end

    Thanks,

    Tigre
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    In the first place I am not sure how your code infers a memory.

    Try instantiate a shift reister in memory using the megawizard.