An important warning confused me--tri-state nodes do not directly drive top-level

Thanks a lot. The 'test.vhd' as list

LIBRARY ieee;

USE ieee.std_logic_arith.all;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_unsigned.all;

ENTITY test IS

PORT(

reset : IN std_logic;

clk : IN std_logic;

enable : IN std_logic;

datain : IN std_logic_vector (7 downto 0);

dataout : OUT std_logic_vector (7 downto 0)

);

END test;

ARCHITECTURE behavior OF test IS

begin

process(reset,clk)

begin

if( reset = '1' ) then

dataout <= (others => '0');

elsif (clk 'event and clk = '1') then

if(enable = '1') then

dataout <= datain ;

else

dataout <= (others => 'Z');

end if;

end if;

end process;

END behavior;