an error about FIR Compiler v8.1

Another question :

A long counter has a long carry chain which will increase the delay.

How to judge a counter is too long for a design?

Does the way to deal with it is to cut the long counter to several shorter counter? Can Quartus automatically do it when performing the synthesis?

Hi tigre,

You have to add that file into your project. It is located in the altera library files under ip\fir_compiler\lib

Hi,

I designed a fir filter using FIR Compiler v8.1 but compilation failed with Modelsim SE.

Compilation message:

vcom -work auk_dspip_lib ..\..\Hdl\SOURCE\RTL\Lib_Altera\auk_dspip_lib_pkg_fir_81.vhd

Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005

-- Loading package standard

** Error: ..\..\Hdl\SOURCE\RTL\Lib_Altera\auk_dspip_lib_pkg_fir_81.vhd(1): expecting: ARCHITECTURE CONFIGURATION ENTITY LIBRARY PACKAGE USE

How to deal with it?

Thanks.

this HDL file is encrypted. you should make sure you generate your FIR with the generate simulation model option checked and compile that for your simulation. if you're using VHDL the file will be <FIR instance name>.vho

you could also do a gate level rather than RTL simulation but that would be slow.