ALU in VHDL newbi having some major issues

You cannot instantiate a component inside a process. A process decribes logic behaviour, and an entity instantiation is like placing a chip on a board. You wouldnt expect to place and remove chips on your board during runtime would you? Entities must be instantiated outside a process.

Other notes:

1. << and >> are not operators in VHDL. If you insist on using std_logic_vectors for numbers, you will have to do the shift manually:

result <=a (30 downto 0) & '0';

But if you want to do things with correct types, ditch the non-standard std_logic_arith and std_logic_unsigned libraries, and use the VHDL library numeric_std instead. With this, you can declare a and b unsigned (or typecast the std_logic_vector to unsigned) then do a bit shift:

result <= std_logic_vector( unsigned(a) sll 1 ); --shift left logical

result <= std_logic_vector( unsigned(b) srl 1 ); --shift right logical