Altpll using output frequency

Dear,

When compiling a simple project with the attached pll as a toplevel i get the following error because i try to use output frequence parameter in stead of device and multiply parameters.

Q9.1--> Error: PLL "altpll:altpll_component|altpll_ign2:auto_generated|pll1" has port CLK[0] connected but parameters clk0_multiply_by and/or clk0_divide_by are either unspecified or set to 0

I really want to define the output frequency in stead of devision and multiply factors.

Can somebody make this work?

Thx,

Johannes

more info:

I want to create a pll based on a vhdl file not using the gui because I want to do batch compilation of pll's with different output frequency settings.

This is what i did: I started from a megawizard generated file. The project compiles fine. I looked in the autamtically generated file and saw that a clock devision and multiplier parameter was created (although is specified a frequency in the megawizard):

"

clk0_divide_by : NATURAL;

clk0_multiply_by : NATURAL;

"

I'd like to work with the output frequency parameter instead as stated in the "The Phase-Locked Loop (ALTPLL) Megafunction User Guide"

"CLK[]_OUTPUT_FREQUENCY: Integer:

Specifies the output frequency of the corresponding output clock port, CLK[9..0].This parameter is ignored if the corresponding CLK[9..0] port is not used. This parameter is unavailable if multiplication or division factors are specified. If omitted, the default is 0."

When compiling a simple project with the attached pll as a toplevel i get the following error:

--> Error: PLL "altpll:altpll_component|altpll_ign2:auto_generated|pll1" has port CLK[0] connected but parameters clk0_multiply_by and/or clk0_divide_by are either unspecified or set to 0

I guess it has something to do with the statement in the user guide at the devide/multiply paramerters:

"Specifies the integer division factor for the VCO frequency of the corresponding output clock port, CLK[9..0] port. The parameter value must be greater than 0. Specify this parameter only if the corresponding CLK[9..0] port is used; however, it is not required if a clock settings assignment is specified for the corresponding clk[9..0] port. If omitted, the default is 0."

What Clock Settings assignment????

Kind regards,

Johannes