Forum Discussion
Altera_Forum
Honored Contributor
9 years agohello vish2648
I have faced the same problem with you. I think you also use the library in modelsim.(Compile->StartSimulation Windows: In "Design" choose the tb file; In "Libraries" SearchLibraries->add: add the suitable library-> OK) This problem may be caused when verilog is used  in the IP but the VHDL library is choosed.  for example library altera: altera is VHDL library                      altera_ver(*_ver) is verilog library. Though it is too late to write back to you. Wish you solve this problem. Forgive me the poor English. Myy