I am using Terasic DE3 340 board which supports LVDS input and output. When I assigned the location for altpll input as a specific pin in Assignment Editor, it gave the following error on compiling: Error: Can't place input clock pin clock driving fast PLL alt_pll:comb_4|altpll:altpll_component|alt_pll_altpll:auto_generated|pll1 in non-compensated I/O location AJ31 -- fast PLL drives at least one non-DPA-mode SERDES Is it not possible to take an LVDS signal as input to altpll ?

Don't lock it down and see where it puts it. The LVDS blocks generally use a Fast PLL, which is a very low jitter, dedicated PLL to make your interface work. The timing is quite tight and needs a very strict relationship between clock and data(I say it's tight, but I actually don't know what speeds you're running at.) The Fast PLL has dedicated clock pins that drive it. If you bring the clock in on other pins, then they delay from that pin to the PLL will use local, non-compensated routing, rather than the path specifically laid out for this type of interface.

How can I check which pin has been automatically assigned by the fitter? It does not show up in the Assignment editor...

The Assignment Editor shows only the user-entered assignments, not what Quartus actually did. All pin locations used by the Fitter are shown in the pin tables in the Fitter compilation report and in the .pin file. The "All Package Pins" table and the .pin file indicate if the Fitter used the location because of an user assignment or if the Fitter chose the location on its own. Another place to look is the Pin Planner. Use "View --> Show --> Show Fitter Placements."

It shows the clock to be assigned to pin W33. now when I check the datasheet for the location of W33, I cannot find the pin number. Is it a flaw in the datasheet? The assignment for input signal is shown to be at AA33 which according to datasheet is a USB controller input pin. When I try to set the assignment of input signal to a location I want that according to the manual supports LVDS input and has a SERDES circuitry, I receive the following error: Error: Can't place differential I/O receiver pin inp in location B25 -- differential I/O pin requires dedicated I/O SERDES, but location does not have differential I/O receiver SERDES available I am now confused how to assign the pins, and whether to trust the user manual of the fpga, or not

Which datasheet are you looking at? I'm guessing it's the Terasic datasheet? That probably doesn't have all the ports available on the FPGA, just the pins brought out on their board. But when you have a floating port(no location assignment), Quartus has no idea what your board is, and may use a port that isn't connected on the board. How are you actually bringing the clock in? Is it something you're hooking up to a general I/O, or is it an existing clock on the board coming in(in which case you have no flexibility). Are you sure the board was designed for this interface?

altpll function | Altera Community

13 Replies

Altera_Forum
Honored Contributor
17 years ago
The HSTC connectors are connected to dedicated clocks: CLK 5,7,13 and 15 (according to pin mapping). Now the PLLs that can take these clocks as input are B1, B2, T1 and T2.
(according to altera handbook)

According to this, I understand that I will have to use top and bottom PLLs if I want to use the LVDS clock inputs from HSTC. However the only configuration that works in altpll function is Left-Right PLL (Even Auto doesnt work)....By not working, I mean that I get an error:
error: the serdes receiver or transmitter atom "rx[0]" has one or more clock and enable ports that are not driven by a fast pll

This may be due to the fact that Top-Bottom PLL do not support LVDS clock network compensation (Source: Altera handbook)

Does this mean I cannot use the HSTC clock pins to drive an external PLL for SERDES function..?
Altera_Forum
Honored Contributor
17 years ago
You are right in so far, as the HSTC connector clock inputs can't drive a Left/Right PLL (PLL with DPA cricuit) directly. That's somewhat surprizing, I don't know DE-340 architecture good enough to decide if it's a well thought design decision or just ill-considered.

However, they can be used by cascading a Top/Bottom PLL and a Left/Right PLL.
Altera_Forum
Honored Contributor
17 years ago
--- Quote Start ---
You are right in so far, as the HSTC connector clock inputs can't drive a Left/Right PLL (PLL with DPA cricuit) directly. That's somewhat surprizing, I don't know DE-340 architecture good enough to decide if it's a well thought design decision or just ill-considered.
--- Quote End ---

I wouldn't be surprised. Most Terasic boards have similar issues regarding clock inputs and outputs pinout. In the DE-1 and DE-2 is even worse because of the limitations of the Cyclone II PLLs.

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altpll function

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