Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

altpll function

I am using Terasic DE3 340 board which supports LVDS input and output. When I assigned the location for altpll input as a specific pin in Assignment Editor, it gave the following error on compilin...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

The HSTC connectors are connected to dedicated clocks: CLK 5,7,13 and 15 (according to pin mapping). Now the PLLs that can take these clocks as input are B1, B2, T1 and T2.

(according to altera handbook)

According to this, I understand that I will have to use top and bottom PLLs if I want to use the LVDS clock inputs from HSTC. However the only configuration that works in altpll function is Left-Right PLL (Even Auto doesnt work)....By not working, I mean that I get an error:

error: the serdes receiver or transmitter atom "rx[0]" has one or more clock and enable ports that are not driven by a fast pll

This may be due to the fact that Top-Bottom PLL do not support LVDS clock network compensation (Source: Altera handbook)

Does this mean I cannot use the HSTC clock pins to drive an external PLL for SERDES function..?