altpll function

Here's what I found out:

I am getting the above errors only if I use the altlvds and altpll (as an external pll to the altlvds function).

I have to choose the 'Left-Right PLL' option in the altpll function otherwise I get an error saying 'One or more enable or clock ports of lvds function are not driven by a fast pll', which means that Top-Bottom is not a fast pll.

And since I am using the Left-right pll, maybe I am not allowed to use the HSTC bank 2 and 3 pins(which is strange). Am I right?

Once I remove the altlvds and altpll function and do a manual deserialization of data, i get no such errors during the assignment since I do not use any pll.