Maybe the outputs are undefined because you haven't run the simulation long enough for the PLL simulation model to simulate the PLL locking. It won't necessarily take as long as it takes the real hardware to lock, but as I recall it can take multiple clock cycles.
If the "fatal error" was an internal error, you should file a service request. If it was a regular error message in the Quartus GUI, try right clicking the message and selecting Help. Sometimes the help pages for messages give you the clue you need to figure out the cause.