Honored Contributor
Honored ContributorI am glad to receive a quick response from you.
Ya you are right its 840MHz. But in my design I have used 'output data rate' is 1000Mbps and a deserilization factor of 10 hence the input clock frequency is 100Mhz and out clock frequency is 1Ghz (which is not possibe as it is limitted to a maximum of 717 Mhz). Therefore I have used a outclock divide factor of 10. The issue is resolved ;). The problem was when I tried to simulate my project in Modelsim the Stratix PLL was not getting locked with the incoming clock. A friend of mine suggested me to change time to 1ps before simulation. Now, the Stratix PLL is locked to the incoming clock and it is working fine. Thanku very much reg Sandeep
