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Altera_Forum
Honored Contributor
12 years agoThe following code works in Quartus and simulates correctly. I will download it to a DE1 board tmorrow to see if it works on the hardware.
module rom_verilog_mif ( input [3:0] addr_a, input clk, output reg [7:0] q_a ); reg [7:0] rom[0:15]; initial begin $readmemh("memory.mif", rom); end always @ (posedge clk) begin q_a <= rom[addr_a]; end endmodule