Forum Discussion
Altera_Forum
Honored Contributor
12 years agoYou can have a look at this document (http://www.altera.com/literature/hb/qts/qts_qii51007.pdf), on pages 14-33 and over. It looks like there is a way to read an initialization file in Verilog, but not in VHDL. You'll probably have to write the whole contents as an VHDL array, as described on example 14-30.
(as a sidenote, srecord (http://srecord.sourceforge.net/) is a tool that can convert from and to lots of different EEPROM formats, and it can generate a VHDL table for you from a .hex or .mif file)