dsun01
Contributor
3 years agoaltera_reserved_tck in timing analysis failure
Dear Intel Support/Expert,
I am compiling hip_a10gx_g3x8_avmm_dma256_1602 with Quartus Prime Pro 21.3. after update the IP and minor tune up, it compiles. but it has few timing analysis failures.
most of the failure is the signal between the launch clock top|emif_0\emif_0_core_usr_clk and latch clock altera_reserved_tck
couldn't find altera_reserved_tck in the design because it is a hidden signal. if it is for the system configuration only, I don't think it has any relation to emif interface, in this case, is it reasonable to set these clock pair as false path? if not, how to optimize this path timing?
thank you very much