altera_reserved_tck in timing analysis failure

I routinely include these commands in my .sdc file to mitigate timing paths related to the system clock and the JTAG clock:

# setup JTAG clock
set_false_path -from [get_ports {altera_reserved_*}] -to CPUCLK
set_false_path -from CPUCLK -to [get_ports {altera_reserved_*}]
create_clock -name altera_reserved_tck -period 40 {altera_reserved_tck}
remove_input_delay [get_ports {altera_reserved_tdi altera_reserved_tms}]
set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports {altera_reserved_tdi altera_reserved_tms}]
remove_output_delay [get_ports {altera_reserved_tdo}]
set_output_delay -clock altera_reserved_tck 3 [get_ports {altera_reserved_tdo}]

# Cut off paths between async clock domains
remove_clock_groups -all
set_clock_groups -asynchronous -group {CLOCK_50} -group {CPUCLK} -group {altera_reserved_tck}