Forum Discussion
dsun01
Contributor
Contributoraltera_reserved_tck in timing analysis failure
Dear Intel Support/Expert,
I am compiling hip_a10gx_g3x8_avmm_dma256_1602 with Quartus Prime Pro 21.3. after update the IP and minor tune up, it compiles. but it has few timing analysis failures. ...
FvM
Super Contributor
Super Contributorjtag_clk is used in alt_sld debug functions which have been intentionally added to the design. Please check in which design entity the timing failing happens and why it involves a transfer between core and jtag clock.
