ALTERA QUARTUS II

Hai,

** Error: C:/Users/user/Desktop/FPGA TESTING_INTEG NODE/INTEG NODE TOP MODULE 6JAN2021/INTEG_TOP_MODULE.vhd(234): Signal 'wrfull_sig' must have only one source since it is connected to buffer port 'wrfull_sig'.

I am doing code in VHDL.

I am using more than one VHDL file and added it to the main project folder.

I am using this wrfull_sig in 3 of the individual projects and used this signal in my main project.

I have assigned wrfull_sig as a buffer in all these 3 projects. Now, this showing this error.

Can you please find a way to resolve this problem

Please give a way to resolve this problem