Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Altera Quartus II Error

i am using the cyclone III Altera with Quartus II and my system specifications are 1 GB RAM, 500 GB Hard disk and Intel dual core processor, i am trying to implement Smwedly model of power converter, the error i am facing is

" error: quartus ii fitter was unsuccessful. 2 errors, 17 warnings

info: allocated 151 megabytes of memory during processing

error: processing ended: fri july 05 20:31:32 2013

error: elapsed time: 00:00:10

error: quartus ii full compilation was unsuccessful. 2 errors, 17 warnings" "

i am seeking guidelines about the error i am facing is that the RAM ?

please guide

Azhar

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Ia that the complete errpr message? Not really informative..

    I believe there are mire details of the error
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Only thing thats in your message here about memory is the info about how much memory is used, not that memory is the problem

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Thank you very much for help , i am actually beginner so it is quite confusing for me, i am pasting the Error again following in order to seek help

    Info: Found 2 design units, including 1 entities, in source file latchSR.vhd

    Info: Found design unit 1: latchSR-rtl

    Info: Found entity 1: latchSR

    Error (10430): VHDL Primary Unit Declaration error at modulatore30aprile.vhd(devil): primary unit "modulatore30aprile" already exists in library "work"

    Info (10499): VHDL information at azhar.vhd(devil): object "modulatore30aprile" is declared here

    Info: Found 0 design units, including 0 entities, in source file modulatore30aprile.vhd

    Info: Found 2 design units, including 1 entities, in source file modulatore30apriletest.vhd

    Info: Found design unit 1: modulatore30apriletest-architettura1

    Info: Found entity 1: modulatore30apriletest

    Error (10430): VHDL Primary Unit Declaration error at modulatore_finale.vhd(devil): primary unit "modulatore_finale" already exists in library "work"Info: Found 2 design units, including 1 entities, in source file sel_shift.vhd

    Info: Found design unit 1: sel_shift-scalamento

    Info: Found entity 1: sel_shift

    Info: Found 2 design units, including 0 entities, in source file sine_package.vhd

    Info: Found design unit 1: sine_package

    Info: Found design unit 2: sine_package-body

    Info: Found 2 design units, including 1 entities, in source file sine_wave.vhd

    Info: Found design unit 1: sine_wave-arch1

    Info: Found entity 1: sine_wave

    Info: Found 2 design units, including 1 entities, in source file sinewavecomplex.vhd

    Info: Found design unit 1: sinewavecomplex-arch11

    Info: Found entity 1: sinewavecomplex

    Info: Found 2 design units, including 1 entities, in source file Vhdl2.vhd

    Info: Found design unit 1: vhdl2-rtl

    Info: Found entity 1: vhdl2

    Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings

    Info: Allocated 151 megabytes of memory during processing

    Error: Processing ended: Mon Jul 08 15:31:40 2013

    Error: Elapsed time: 00:00:02

    Error: Quartus II Full Compilation was unsuccessful. 2 errors, 0 warnings

    can you please help?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Hello,

    Thank you very much for help , actually i am beginner so it is quite confusing for me,

    here i am pasting the Errors again in order to seek help

    Info: Found 2 design units, including 1 entities, in source file latchSR.vhd

    Info: Found design unit 1: latchSR-rtl

    Info: Found entity 1: latchSR

    Error (10430): VHDL Primary Unit Declaration error at modulatore30aprile.vhd(devil): primary unit "modulatore30aprile" already exists in library "work"

    Info (10499): VHDL information at azhar.vhd(devil): object "modulatore30aprile" is declared here

    Info: Found 0 design units, including 0 entities, in source file modulatore30aprile.vhd

    Info: Found 2 design units, including 1 entities, in source file modulatore30apriletest.vhd

    Info: Found design unit 1: modulatore30apriletest-architettura1

    Info: Found entity 1: modulatore30apriletest

    Error (10430): VHDL Primary Unit Declaration error at modulatore_finale.vhd(devil): primary unit "modulatore_finale" already exists in library "work"Info: Found 2 design units, including 1 entities, in source file sel_shift.vhd

    Info: Found design unit 1: sel_shift-scalamento

    Info: Found entity 1: sel_shift

    Info: Found 2 design units, including 0 entities, in source file sine_package.vhd

    Info: Found design unit 1: sine_package

    Info: Found design unit 2: sine_package-body

    Info: Found 2 design units, including 1 entities, in source file sine_wave.vhd

    Info: Found design unit 1: sine_wave-arch1

    Info: Found entity 1: sine_wave

    Info: Found 2 design units, including 1 entities, in source file sinewavecomplex.vhd

    Info: Found design unit 1: sinewavecomplex-arch11

    Info: Found entity 1: sinewavecomplex

    Info: Found 2 design units, including 1 entities, in source file Vhdl2.vhd

    Info: Found design unit 1: vhdl2-rtl

    Info: Found entity 1: vhdl2

    Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings

    Info: Allocated 151 megabytes of memory during processing

    Error: Processing ended: Mon Jul 08 15:31:40 2013

    Error: Elapsed time: 00:00:02

    Error: Quartus II Full Compilation was unsuccessful. 2 errors, 0 warnings

    could you please help?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    I am not sure, but it might be that you have included some entities or files with the same names in your project.

    Quartus doesn't know which one it needs to use than.

    modulatore30aprile

    modulatore_finale

    Those are the ones declared twice if I understand the message correctly