Altera FPGA ring oscillator low level implementation

--Here is a better code with generate

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY forced_delay IS

GENERIC (N : INTEGER := 20); --number of forced delay buffers

PORT (

din : IN STD_LOGIC;

dout : OUT STD_LOGIC);

END forced_delay;

ARCHITECTURE arch OF forced_delay IS

SIGNAL a:STD_LOGIC_VECTOR (N downto 1);

COMPONENT LCELL

PORT (

a_in : IN STD_LOGIC;

a_out : OUT STD_LOGIC);

END COMPONENT;

BEGIN

LC_1: LCELL PORT MAP(a_in=>din,a_out=>a(1));

Gen_delay : FOR i in 1 to N-1 GENERATE

LC : LCELL PORT MAP(a_in=>a(i),a_out=>a(i+1));

END GENERATE;

dout<=a(N);

END arch;