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Altera_Forum
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18 years ago

Altera FPGA ring oscillator low level implementation

Hi all, I'm a student working on a summer research project. I've been stuck on the same problem for some time now and would greatly appreciate any help. Software/Hardware: Quartus II so...
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Altera_Forum
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18 years ago

I had a colleague who was trying to implement delays in a MAX CPLD with LCELLs, and the synthesis setting to "Ignore LCELL" was set to AUTO, which bascially meant ON (ignore)

So he set it to OFF (don't ignore my LCELLs!) and it worked.