Altera FPGA ring oscillator low level implementation

The LCELL states that it is the output of a logic cell. That doesn't mean the lcell can't be packed with functionality. (This was what I was stating earlier but throws everyone off.) So if you're a_in port gets the AND of two signals, that AND gate will get put into the LCELL. So the LCELL primitive doesn't represent an actual LUT, but just that it's the output of a LUT. So you should be able to do whatever logic the reset does to the oscillating signal and then drive that into the a_in port of the LCELL.