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Altera_Forum
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18 years ago

Altera FPGA ring oscillator low level implementation

Hi all, I'm a student working on a summer research project. I've been stuck on the same problem for some time now and would greatly appreciate any help. Software/Hardware: Quartus II so...
Altera_Forum's avatar
Altera_Forum
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18 years ago

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You should also be able to put them all into a LogicLock region, so the fitter chooses their final placement within a lab and where the lab goes, but will keep them all in the same lab.

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But remember that different placement within the LAB from one ring instance to the next could result in timing differences that will mask any differences from on-chip process variation.