Forum Discussion
Altera_Forum
Honored Contributor
18 years ago --- Quote Start --- Do I need to use an LCELL to implement the functions and not LUT_input/LUT_output? Also do you guys know of a way that I can verify that the placements are actually still there after synthesis. At this point it compiles without error, but with that warning. Is there a way that I can see that the placements have been respected? --- Quote End --- I haven't heard of LUT_input/LUT_output primitives. I use LCELL to do what Rysc said. Be sure "Ignore LCELL Buffers" is off (the default) in the "More Analysis & Synthesis Settings" dialog box. You might also need "Remove Redundant Logic Cells" to be off. I don't know that all kinds of unused location assignments produce your Fitter warning below, but at least you know yours do. Just check for the warning. If you still want to know for certain whether something was placed where you want it, check "Tools --> Chip Planner" or "Assignments --> Timing Closure Floorplan". Warning: Ignored locations or region assignments to the following nodes