Altera FPGA ring oscillator low level implementation

Instantiate multiple LCELLs together. I believe in VHDL the ports are a_in and a_out(both std_logic). Note that an LCELL is not an empty logic cell. Instead it designates that that particular point will be the output of a logic cell. So, for example, if you have an AND gate that feeds an output pin and insert an LCELL, the LCELL won't do anything since the AND gate would already be the output of a logic cell. But if you chain two LCELLs, then you'll have an AND gate followed by an empty cell. (I've seen confusion over this, but the way LCELL works is nice for control). Anyway, just chain a bunch of them together.