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Altera_Forum
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18 years ago

Altera FPGA ring oscillator low level implementation

Hi all, I'm a student working on a summer research project. I've been stuck on the same problem for some time now and would greatly appreciate any help. Software/Hardware: Quartus II so...
Altera_Forum's avatar
Altera_Forum
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18 years ago

The systhesis tool is optimizing the redundent buffers away, etc.

Try either a keep attribute, or try also feeding each buffer output off the chip so that the tool is forced to keep each node in the design.

Do not let the tool 'help' you so much.

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ps. Forum rules ask that you not multiply post the same question to different sub forums.

Thanks.